Driving pulses
The TCD1304 requires 3 driving pulses:
The following is for STM32F40x firmwares. If you use the STM32F103 make sure to also read the final paragraph.
MCLK – The master clock
The MCLK (sometimes called fM or φM) is the CCD’s clock speed. It defines the time-base which the TCD1304 operates in, and for the unmodified CCD driver firmware MCLK has the value:
MCLK = 2.0 MHz
The value of MCLK is used to derive the integration time from the SH pulse.
SH – The shift gate
The SH pulse defines the integration time (tint), which for the TCD1304 cannot be shorter than 10 µs. The user controls the SH period, which together with MCLK, determines the frequency of the SH pulse:
SH-frequency = MCLK / SH-period
tint = 1 / SH-frequency = SH-period / MCLK
Because the CCD has a minimum integration time of 10 µs, the SH period cannot be smaller than:
SH-period = tint × MCLK = 10 µs × 2.0 MHz = 20
Because the timer controlling SH is 32-bit, the largest value for SH-period is
2³² – 1 = 4294967295
Corresponding to a maximum integration time of
tint = (2³² – 1) / 2.0 MHz = 35 min
Example:
Say one wishes to make a collection with an integration time of 15 ms. Then:
SH-period = tint × MCLK = 15 ms × 2.0 MHz = 30000
ICG – The integration clear gate
The ICG pulse defines the moment when the pixels are dumped to the output pin. The ICG pulse must coincide with an SH pulse:
ICG-period = n × SH-period
where n is an integer. When n = 1, the CCD is in normal mode. When n > 1, it runs in electronic shutter mode.
Because it takes 4 MCLK cycles to output 1 pixel, and the chip has 3694 pixels, the minimum ICG-period is
4 × 3694 = 14776
This defines the readout time:
tread = 14776 / 2.0 MHz = 7.4 ms
In the unmodified firmware, the user LED blinks at half the ICG frequency.
STM32F103 specifics
MCLK = 800 kHz
Since timers are 16-bit, max SH/ICG = 65535
tint = 65535 / 800 kHz = 82 ms
Minimum ICG = 14776
Minimum SH = 10 µs × 800 kHz = 8